1. Field of the Invention
The present invention relates to a method of fabricating a high-voltage CMOS device, by which an extended drain region fails to enclose a heavily-doped drain region.
2. Discussion of the Related Art
Generally, a power MOSFET device has a switching speed superior to that of other power devices and is characterized in having low ON-resistance of a device having a relatively low strength voltage below 300V, and a high-voltage lateral power MOSFET becomes popular as a high-integration power device.
There are various high-voltage power devices such as DMOSFET (double-diffused MOSFET), insulated gate bipolar transistor, EDMOSFET (extended drain MOSFET), LDMOSFET (lateral double-diffused MOSFET), etc.
Specifically, LDMOSFET is variously applicable to HSD (high side driver), LSD (low side driver), H-bridge circuit, and the like and its fabrication is facilitated. Yet, in the LDMOSFET, a doping density of a channel region is structurally uneven to bring a high threshold voltage thereof and breakdown takes place on s silicon substrate surface of a drift region in the vicinity of the channel region.
FIG. 1 is a cross-sectional diagram of a high-voltage CMOS transistor according to a related art.
Referring to FIG. 1, a lightly-doped extended N type drain 12 is formed in a P type substrate 11. And, a highly doped N+ type drain is sufficiently distant from a source 14 to provide a high strength voltage even if a high voltage is applied to a drain 13.
However, a current flow path appears on a surface region of the above-configured high-voltage CMOS transistor. As the high voltage is applied to the drain, an electric field is focused on a surface junction 15 between the extended N type drain and the P type substrate. Hence, both of the high current migration and the electric field concentration take place simultaneously to degrade device reliability due to the corresponding colliding ionization. Moreover, breakdown occurs on a semiconductor surface to lower the device reliability as well.